A wafer has been known for a semiconductor device where an oxide layer, a lower resist layer formed of an organic layer, a bottom anti-reflective coating (BARC) layer, etc., are stacked on a silicon substrate. In this configuration, the lower resist layer serves as a mask layer when the oxide layer is etched.
In recent use, while the miniaturization of the semiconductor device is progressed, a narrow pitch structure where the interval between holes is narrow has been applied in order to more finely form circuit patterns on a surface of the wafer. In order to form the circuit patterns having the narrow pitch structure, during the manufacturing process of the semiconductor device, there is a need to make the minimum dimension of patterns in the lower resist layer (hereinafter, referred to as a ‘mask layer’) formed with an organic layer small, and accurately transfer a small-dimensional opening part (hole) to the oxide layer that is a target layer to be processed.
In the substrate processing method processing the wafer including the amorphous carbon layer (hereinafter, referred to as an ‘ACL layer’) serving as the mask layer, a technology has been proposed for etching the ACL layer at a high etching rate and a high selectivity. See, for example, Publication of Japanese Patent Application Laid-Open No. 2007-180358.
However, the related art does not suggest any solutions to prevent the occurrence of bowing where a portion of a cross section of a hole expands in a mask layer. Accordingly, a hole shape of the mask layer which is an ACL layer becomes a bowing shape, such that the quantity of the remaining ACL layer becomes insufficient. Further, the ACL layer located between adjacent holes is collapsed to close the opening part of the hole, causing a case where the oxide layer that is a target layer to be processed may not be etched, which is problematic.